`include "../define.svh"
module Adder_top (
    input clk,
    input sys_rst_n,
    input valid1,
    input valid2,
    input [1:0]data_type,  
    input signed [`DATA_SIZE-1:0]a_in,
    input signed [`DATA_SIZE-1:0]b_in,
    input mix_precision,
    output [`DATA_SIZE-1:0]float_o,
    output adder_valid //连接下一级加法器的valid端
);
/*     reg [`DATA_SIZE-1:0]a_in;
    reg [`DATA_SIZE-1:0]b_in;
always @(posedge clk) begin
    a_in<=a_in_r;
    b_in<=b_in_r;
end */
    wire en;
    assign en = valid1 && valid2;
    wire int_valid;
    wire [31:0] int_out_reg;
    wire [31:0] fp_out;
    wire fp_valid;
    
    wire [1:0] type_in;
    assign type_in = (mix_precision)? `FP32 : data_type;

    Add_INT_top u_add_int_top(
    .clk(clk),
    .sys_rst_n(sys_rst_n),
    .data_type(type_in),  //2'b00:INT4,2'b01:INT8,2'b10:FP16,2'b11:FP32
    .en(en),
    .a_in(a_in),
    .b_in(b_in),
    .c_out(int_out_reg),
    .c_valid(int_valid)
    );

    Adder_FP_top u_add_fp_top(
    .clk(clk),
    .sys_rst_n(sys_rst_n),
    .valid1(valid1),
    .valid2(valid2),
    .data_type(type_in),  
    .a_in(a_in),
    .b_in(b_in),
    .float_o(fp_out),
    .adder_valid(fp_valid)
);
    assign adder_valid = (type_in[1])? fp_valid : int_valid;
    assign float_o = (type_in[1])? fp_out : int_out_reg;



endmodule